Dynamic random access memory (DRAM) is a type of volatile memory that generally provides high density with sufficient speed. In the quest to achieve even higher density, a technique for one-transistor DRAM cells has been developed. The individual memory cell is provided on a semiconductor-on-insulator (SOI) substrate, requires only a single transistor, and does not require a capacitor, which has historically been used in DRAM cells. This type of DRAM cell is also known as a capacitorless DRAM cell since it does not require a capacitor.
A one-transistor DRAM cell typically includes a top gate, which is situated over the body of the transistor, and a bottom gate, which is situated in a bulk substrate underlying a buried oxide layer in the SOI substrate. The one-transistor DRAM cell can be programmed to a logic “1” or a logic “0” by appropriately biasing the top and bottom gates and the source and drain of the DRAM cell, which causes a corresponding change in the threshold voltage of the top gate. The top gate voltage can be sensed during a read operation to determine if the one-transistor DRAM cell is programmed as a logic “1” or a logic “0.”
The difference in top gate voltage between a logic “1” and a logic “0” can be referred to as the “sensing margin” of the one-transistor DRAM cell. In a conventional one-transistor DRAM cell, the sensing margin is typically too low. As a result, the conventional one-transistor DRAM cell can require complicated sensing circuitry to distinguish a logic “1” from a logic “0,” which can undesirably increase manufacturing cost.